Electronic systems can be employed in environments having higher reliability requirements than typical industrial applications. For example, some applications, such as systems employed in space, can require an integrated circuit be “radiation hardened” (rad hard) with respect to ionizing radiation.
Current space systems are typically designed with integrated circuited devices fabricated on technology nodes several generations behind their commercial counterparts. In the case of systems with memory devices, one conventional approach can incorporate a large number of static random access memory (SRAM) devices having speeds well below their commercial counterparts. Such SRAM devices can be used in parallel (for error correcting/redundancy), requiring a large bus and introducing wait states.
The space community is facing a huge initiative to modernize their electronic design. Conventional high reliability designs have largely been in 100 MHz (clock speed) or less domain. Currently, advances in radiation hardened field programmable gate arrays (FPGAs) have produced high reliability FPGAs operating at clock speeds of 250 MHz to 400 MHz. Conventionally, rad hard memory solutions do not match the performance of such FPGA devices.
A common memory type included in systems is a first-in-first-out (FIFO) memory. A FIFO memory can allow data to be written into and read out from its array at independent data rates. FIFOs are ubiquitous constructs needed for data manipulation tasks such as clock domain crossing and low latency memory buffering.
Monitoring the status of a FIFO memory can be an important feature to avoid any data under or over flows, and is achieved by the full and empty flags. As the name implies, a full flag is asserted when a FIFO memory is full. Similarly, an empty flag is asserted when a FIFO memory is empty. FIG. 18A is a functional block diagram of a typical conventional FIFO memory 1801. A conventional FIFO memory 1801 can include a write port 1803-0 by which data is written into the FIFO memory 1801, and a read port 1803-1 from which data is read. A write operation can be indicated by appropriate control signals at the write port 1803-0 (WENB, WCSB) and the application of input write data (Datain). Control signals and data at write port 1803-0 can be timed according to a write clock WCLK. Write data can be stored in an input register 1809, and then written into a dual port random access memory (DPRAM) array 1811. A write pointer circuit 1807 can generate a sequence of write addresses.
In a similar fashion, a read operation can be indicated by appropriate control signals at the read port 1803-1 (RENB, RCSB) timed according to a read clock RCLK. A read pointer circuit 1815 can generate a sequence of read addresses to access read data. Corresponding read data can be output from DPRAM array 1811 via driver 1821 as output read data (DATAOUT).
DPRAM array 1811 enables independent access to storage locations for input (write) and output (read) ports (1803-0/1) to operate independently. FIFO control logic 1819 can manage read and write pointers to enable first-in-first-out type accesses. Further, FIFO control logic 1819 can assert a full flag (Full) and an empty flag (Empty), if such conditions arise. In addition, FIFO control logic 1819 can assert error flags in the event a read or write access cannot be completed.
FIG. 18B shows state machine logic 1825 for a FIFO, which controls the read and write pointers along with maintaining correct flag logic. In FIG. 18B, an event “Push=1” can correspond to a write operation, while “Pop=1” can correspond to a read operation. Further, state 1827 can result in the assertion of an empty flag, while a state 1829 can result in the assertion of a full flag.
Another important set of flags sometimes implemented with FIFO memories are the almost full and almost empty flags. Such flags can be used by a system to either stop sending (PUSH) or stop receiving (POP) data to ensure data in transit can be properly handled. A value less than the maximum count for almost full and a value greater than zero for almost empty can be used to generate these flags, respectively.
Another common memory type can be a dual port memory. A dual port memory can have two totally independent ports that can have simultaneous access capability to any stored data. Each port can write and read data into and out of any memory location. FIG. 19 is a high level functional block diagram of a conventional synchronous dual port static random access memory (SRAM) 1935.
As can be seen, each port (portL 1903-0 and portR 1903-1) can have its own associated control lines (portL(R)_wr_n, portL(R)_ce_n, portL(R)_rst_n), data lines (portL(R)_io) and address lines (portL(R)_add). Operations are initiated by a low to high transition on the clock signals for each port (portL_clk, portR_clk). Writing to, or reading from, the selected address is controlled by the write/read selection signals (portL_wr_n, portR_wr_n). Output enables (portL_oe_n, portR_oe_n) are asynchronous signals and control the data flow, since inputs/outputs (I/Os) are bi-directional. Chip enables (portL_ce_n, portR_ce_n) are available for ease of depth expansion. Control circuits 1919-0/1 can control accesses for their respective ports. Addresses for different ports (portL(R)_add) can be decoded by corresponding address decoders 1937-0/1. Write data for different ports can be stored in different input registers (1907-0/1) prior to being written into DPRAM array 1911. Similarly, read data for different ports can be stored in output registers 1917-0/1, before being driven on device outputs by corresponding drivers 1921-0/1.
Data collisions between the two ports can occur and is avoided to ensure data integrity. When different data is simultaneously written to the same memory location by both ports (a collision), unknown data ends up being stored (the data can be old, new or transitional data). A similar situation exists when one port is writing data and the other port is reading data simultaneously from the same memory location. Unknown data can be read out (the data can be the old stored data or the newly written data). Arbitration is generally implemented to avoid collisions and in most cases is through customer implemented external logic to the dual port SRAM.